Deep well is frequently used as isolation between noisy and non-noisy region in a chip. For example deep well is used as the isolation of noisy digital block and non-noisy analog block in a chip. However, during fabricating processes including, for example, metal etching and/or via etching, charges are stored in a deep well region. When the fabricating processes are constructed, a potential drop across a gate oxide for a device outside the deep well region is built due to the stored charges. The gate oxide for the device outside the deep well region could be damaged due to the discharged charges.